Arithmetic circuits Binary addition Binary Subtraction Unsigned binary numbers Sign-magnitude numbers 2’S Complement representation 2’S Complement arithmetic Arithmetic building blocks

Powers of 2 Powers of 2 20 21 22 23 24 25 26 27 28 29 210 211 212 213 214 215 216 Decimal Equivalent 1 2 4 8 16 32 64 128 256 512 1,024 2,048 4,096 8,192 16,384 32,768 65,536 Abbreviation 1K 2K 4K 8K 16K 32K 64K

Decimal-Binary Equivalences 1 3 7 15 31 63 127 255 511 1,023 2,047 4,095 8,191 16,383 32,767 65,535 Binary 1 11 111 1111 1 1111 11 1111 111 1111 1111 1111 1 1111 1111 11 1111 1111 111 1111 1111 1111 1111 1111 1 1111 1111 1111 11 1111 1111 1111 111 1111 1111 1111 1111 1111 1111 1111 Hexadecimal 1 3 7 F 1F 3F 7F FF 1FF 3FF 7FF FFF 1FFF 3FFF 7FFF FFFF

Binary addition 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 10 = 0 + carry of 1 into next position 1 + 1 + 1 = 11 = 1 + carry of 1 into next position HALF ADDER A B SUM CO A B SUM CO 1 SUM = (AB) + (AB) Carry-Out = (AB)

1-bit 8 Strings Full Adder with Carry-In and Carry-Out Binary addition 1-bit 8 Strings Full Adder with Carry-In and Carry-Out CI A B SUM CO 1 FULL ADDER A B SUM CO CI SUM = (A B)CI + (A B)CI + Carry-Out = (AB)CI + (A+B)CI

1-bit 8 Strings Full Adder with Carry-In and Carry-Out SUM CO CI SUM = (A B)CI + (A B)CI + Carry-Out = (AB)CI + (A+B)CI

Binary addition

Binary Subtraction 0 - 0 = 0 1 - 0 = 1 1 - 1 = 0 0 - 0 = 0 1 - 0 = 1 1 - 1 = 0 0 - 1 = 1 ต้องยืมจากหลักที่สูงกว่ามา 1 HALF Subtractor A B SUB BO A B SUB BO 1 SUB = Borrow-Out =

1-bit 8 Strings Full Subtractor with Borrow-In and Borrow -Out Binary Subtraction 1-bit 8 Strings Full Subtractor with Borrow-In and Borrow -Out BI A B SUB BO 1 A FULL Subtractor SUB B BO BI SUB = Borrow-Out =

REPRESENTING UNSIGNED NUMBERS (Absolute value) =00H B7 B6 B5 B4 B3 B2 B1 B0 =FFH 1

REPRESENTING SIGNED NUMBERS in sign-magnitude form. =+5210 1 Magnitude = 5210 SIGN BIT B7 B6 B5 B4 B3 B2 B1 B0 =-5210 1 Magnitude = 5210 SIGN BIT

REPRESENTING SIGNED NUMBERS in the 2’ S-complement system. A7 A6 A5 A4 A3 A2 A1 A0 =+4510 1 True binary SIGN BIT B7 B6 B5 B4 B3 B2 B1 B0 =-4510 1 2’s complement SIGN BIT

Range of Sign-Magnitude Numbers =+110 1 B7 B6 B5 B4 B3 B2 B1 B0 =+12710 1 SIGN BIT A7 A6 A5 A4 A3 A2 A1 A0 =-12710 1 B7 B6 B5 B4 B3 B2 B1 B0 =-110 1

Range of Sign-Magnitude Numbers =+110 1 B7 B6 B5 B4 B3 B2 B1 B0 =+12710 1 SIGN BIT A7 A6 A5 A4 A3 A2 A1 A0 =-12710 1 B7 B6 B5 B4 B3 B2 B1 B0 =-110 1

การคอมพลีเมนต์เลขฐานสอง แบ่งออกเป็น คอมพลีเมนต์ 1 (1’s complement) คอมพลีเมนต์ 2 (2’s complement) การคอมพลีเมนต์เลขฐานสองนี้นำไปใช้เกี่ยวกับการคำนวณทางไมโครคอมพิวเตอร์มาก เพราะว่าจะใช้ในลักษณะการลบด้วยวิธีการบวกด้วยคอมพลีเมนต์ สรุป การลบด้วยการบวกด้วยคอมพลีเมนต์นั้นจะทำนองเดียวกับการคอมพลีเมนต์เลขฐานสิบ

การคอมพลีเมนต์เลขฐานสอง X3X2X1X0 = 1000 1’s complement X3X2X1X0 = 0111 X3 X2 X1 X0 2’s complement 2’s complement = 1’s complement + 1

Positive and Negative Numbers -8 -7 -6 -5 -4 -3 -2 -1 0 +1 +2 +3 +4 +5 +6 +7 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 Magnitude Positive Negative 1 2 3 4 5 6 7 8 0001 0010 0011 0100 0101 0110 0111 - 1111 1110 1101 1100 1011 1010 1001 1000

2’ S-complement representation summary Positive numbers always have a sign bit of 0, and negative numbers always have a sign bit of 1. Positive numbers are stored in sign-magnitude form. Negative numbers are stored as 2’s complements. Taking the 2’s complement is equivalent to a sign change.

Example : Binary contents Hexadecimal contents Decimal contents 0001 0100 ____ ____ 1001 1110 ___ ___ ___ ___ 14H DDH ___H BDH 70H 6EH _____H +20 ___ +47 -125 -19,750 1101 1101 -35 0010 1111 2F 1011 1101 -67 9E -98 0111 0000 +112 1000 0011 83 0110 1110 110 1011 0010 1101 1010 B2DA

2’s complement arithmetic ADDITION CASE 1 Both positive. +83 +16 CASE 2 Positive and smaller negative. +125 -68 0111 1101 1011 1100 0101 0011 0001 0000 83 0101 0011 +16 +0001 0000 99 0110 0011 125 0111 1101 +(-68) +1011 1100 57 1 0011 1001 CASE 3 Positive and larger negative. +37 -115 CASE 4 Both negative. -43 -78 1101 0101 1011 0010 0010 0101 1000 1101 -43 1101 0101 +(-78) +1011 0010 -121 1 1000 0111 37 0010 0101 +(-115) +1000 1101 -78 1011 0010

2’s complement arithmetic SUBTRACTION CASE 1 Both positive. +83 +16 CASE 2 Positive and smaller negative. +68 -27 0100 0100 1110 0101 0101 0011 0001 0000 83 0101 0011 +(-16) +1111 0000 67 1 0100 0011 68 0100 0100 +(+27) +0001 1011 95 0101 1111 CASE 3 Positive and larger negative. +14 -108 CASE 4 Both negative. -43 -78 1101 0101 1011 0010 0000 1110 1001 0100 -43 1101 0101 +(+78) +0100 1110 35 1 0010 0011 14 0000 1110 +(+108) +0110 1100 122 0111 1010

Controlled inverter A7-A0 0110 1110 1 Y7-Y0 1001 0001 INVERT INV LOGIC 1 A7-A0 0110 1110 Y7-Y0 1001 0001

Binary adder-subtractor diagram ADD/SUB S8 S7 S6 S5 S4 S3 S2 S1 S0 SUBTRACTION A7 A6 A5 A4 A3 A2 A1 A0 +B7 B6 B5 B4 B3 B2 B1 B0 +1 S7 S6 S5 S4 S3 S2 S1 S0 - - - - - - - - ADDITION A7 A6 A5 A4 A3 A2 A1 A0 +B7 B6 B5 B4 B3 B2 B1 B0 S7 S6 S5 S4 S3 S2 S1 S0

Binary adder-subtractor circuit. 7483 7483