งานนำเสนอเรื่อง: "-- Introduction to Sequential Devices Digital System Design I"— ใบสำเนางานนำเสนอ:
1 -- Introduction to Sequential Devices 04-710-302 Digital System Design I
2 Outline Combinational Circuits vs. Sequential Circuits Flip-Flop Binary cell that can store one bit of information.Basic Flip-Flop CircuitCommon Types of Flip-Flops: RS, JK, D, T.Mealy Machine and Moore MachineDesign Flow of Sequential SystemSynthesis and OptimizationExamples
3 Combinational Circuits A circuit is combinational if it computes a function which depends only on the current inputs applied to the circuit; for every input set of values, there is a unique output set of values.Acyclic circuits are necessarily combinationalCyclic circuits can be combinationalin fact, there are combinational circuits whose minimal implementation must have cycles [Kautz 1970]
4 Sequential CircuitsIn a sequential circuit, the output values may be different for the same set of input values; the output depends on the current contents of memory elements as well.Feedback (cyclic) is a necessary condition for a circuit to be sequential.Synthesis of sequential circuits is not as well developed as combinational. (only small circuits)Sequential synthesis techniques are not really used in commercial software (except maybe retiming).
14 Basic Flip-Flop Two Output (Q and Q’) Various Ways to Feed Flip-Flops NOR Gate Flip-FlopsQSQ’R12NAND Gate Flip-FlopsQRQ’S12SRQQ’1SRQQ’1
15 RS Flip-Flop > S Q S Q CP Q’ R Q’ R Three Inputs: Four States: 3 1 234QSQCP>Q’RQ’RThree Inputs:Clock Pulse: additional input to control when state is changing.S(et) inputR(eset) inputFour States:Set state: S=1, R=0, CP=1 (Q=1, Q’=0)Reset state: S=0, R=1, CP=1 (Q=0, Q’=1)Indetermined: S=1, R=1, CP=1 (Q=1, Q’=1)No change: S=0, R=0, CP=1
20 D Flip-Flop > Two Inputs: Two States: Characteristic Equation: D Q 1234QCPDQ>Q’Q’Two Inputs:CP: Clock PulseD: Set inputD’: Reset inputTwo States:Set state: D=1, CP=1Reset state: D=0, CP=1Characteristic Equation:Q(t+1) = F(Q(t), D(t+1)) = D
21 T Flip-Flop > One input JK flip-flop Two States: 31QTQCP>Q’Q’24One input JK flip-flopTwo States:No Change: T=0, CP=1Complement: T=1, CP=1Characteristic Equation:Q(t+1) = F(Q(t), T(t+1)) = TQ’+T’Q
22 Excitation TableExcitation table: the reverse of characteristic table, indicates how we should change flip-flop inputs to make the required state transition.SRQQ(t+1)1i.d.Q(t)Q(t+1)SRx1excitation tablecharacteristic table
24 State, State Reduction and Assignment A state of a sequential circuit is defined by the binary information stored in the memory elements (e.g. flip-flop).One flip-flop stores one bit, so m flip-flops can define at most 2m states.Two states are equivalent if for any input, they produce the same outputs and move to the same or equivalent states.State Reduction problem: reduce the number of flip-flops in a sequential circuit.State Assignment problem: assign binary values to states such that the cost of the flip-flop input functions is reduced.
26 Mealy and Moore ModelsA sequential system is of Mealy type if output values depend on both present states and inputs.Recall that a state is a combination of the memory element’s content.A sequential system is of Moore type if output values depend only on the present states.This does not mean that output is independent of the inputs. Instead, the impact is through memory units.
28 Example: Sequential System Design System spec. → state transition table/graphDesign a circuit with one input x and three outputs A,B,C. An external source feeds x one bit per clock cycle, when x=0, the outputs remain no change; otherwise, they repeat the binary sequence: 0,1,3,7,6,4, one at a time.current statenext statex= x=1ABC10/0001/001S1S2S3S4S5S61/0111/1111/1101/1001/0000/0010/0110/1000/1100/111
29 Example: Sequential System Design State Minimization/ReductionRecall that two states are equivalent if for any input, they produce the same outputs and move to the same or equivalent states. We need only one state for all its equivalent states. Therefore, redundant states can be removed and hardware (e.g. flip-flops) can be saved.001011011/10/00/11/00011011/10/00/11/01001=
30 Example: Sequential System Design State Assignment/EncodingThe goal is to assign binary values, each bit will be implemented by one flip-flop, to states.Sequential binary assignment:S1=001, S2=010, S3=011S4=100, S5=101, S6=110Average bits to be changed:[(0+2)+(0+1)+(0+3)+(0+1)+ (0+2)+(0+3)]/12 = 1Ad hoc binary assignment:S1=000, S2=001, S3=011S4=111, S5=110, S6=100[(0+1)+(0+1)+(0+1)+(0+1)+(0+1)+(0+1)]/12 = 0.50/0001/001S1S2S3S4S5S61/0111/1111/1101/1001/0000/0010/0110/1000/1100/111
31 Example: Sequential System Design System spec. → state transition table/graph→ state minimization/encoding→ flip-flop selection→ excitation/output table derivation001011011/10/00/11/0CurrentStateInOutABxTATBy1NextStateFlip-flopinputsQ(t)Q(t+1)T1
32 Example: Sequential System Design System spec. → state transition table/graph→ state minimization/encoding→ flip-flop selection→ excitation/output table derivation→ logic simplification/minimization→ logic diagram drawingFlip-flop input functions:TA = A BTB = (Ax)’Output:y = ABx001011011/10/00/11/0T>QQ’BACPxy