Memory Management Ex. C = A + B A typical instruction-execution cycle

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1 Memory Management Ex. C = A + B A typical instruction-execution cycle
1. Instruction fetch (read instr from mem) 2. Instruction decode (read operands from mem) 3. Execute 4. Mem (writing result to mem) 5. Write back (to register) Memory and registers are only device that CPU can access directly. We are interested only in sequence of memory addresses generated by the running program, not how they are generated.

2 How to separate memory space?
Base register from to 42093 Limit register pp. 316

3 Loaded by privileged instructions (kernel mode)
Memory Protection Loaded by privileged instructions (kernel mode) pp. 317

4 Location-dependent executable code
ld r // data segment (variable A) ld r // data segment (variable B) add r0 r1 r2 st r // data segment (variable C = A + B) J // code segment This program assumes that base address is zero. If not, the program may encounter illegal memory access. ld 1 ld Code segment 2 add 3 st Stack segment (for recursive call) 4 j … 100 C Data segment 101 A 102 B

5 Memory-management Unit
Logical Address vs. Physical Address Logical address must begin from zero. Memory-management Unit pp. 320

6 Address Binding - Compile time - Load time - Execution time (swapping)
main.c Address Binding - Compile time - Load time - Execution time (swapping) f1.o f2.o printf printf pp. 319

7 Summary Logical address: memory address issued by CPU
Physical address: memory address issued by MMU Address binding: logical → physical Compile time binding at compilation Load time binding at loading into memory (1 time) SW loader will change executable codes HW relocation (base) register in MMU (slide 5) Execution time binding at swapping into memory (many times)

8 Dynamic Loading Load main function into memory.
Load other functions on demand. This method is particularly useful when large amounts of code are needed to handle infrequently occurring cases, such as error routines. There may be multiple copies of the same routine in memory.

9 There is only single copy of f1() and f2() in memory.
Dynamic Linking and Shared Libraries Static linking exe = main.o + f1.o + f2.o Dynamic linking exe = main.o + stub1 + stub2 Before calling After calling main() { call stub1() call stub2() } stub1() { locate library } stub2() { locate library } main() { call stub1() call stub2() } f1() { } f2() { } There is only single copy of f1() and f2() in memory.

10 Swapping pp. 322

11 Memory Mapping and Protection
contiguous Memory Mapping and Protection pp. 325

12 Memory Allocation Process 1 Process 5 Process 2 Process 6 Process 3
Input queue (waiting processes) Hole Process 5 Process 2 Process 6 Long-term Scheduler Process 3 Process 7 First Fit Best Fit Worst Fit Process 4 Process 8

13 Fragmentation External fragmentation Holes in memory.
Compaction (possible if relocation is dynamic, hw-supported) Non-contiguous logical space (paging & segmentation) 50-percent rule (first fit), given n blocks allocated, 0.5n will be lost. One-third of memory may be unusable. Internal fragmentation (unused = เศษของ block) unused memory that is internal to a partition. Hole Starting position Size 1 0x 2 bytes 2 0x00AB0000 200 MB 3 0x07F00000 1000 MB The overhead to keep track of this hole is larger than the hole itself. Allocate by equal-size block (page). Hex.

14 Paging Frame fixed-size block on physical memory
Page fixed-size block on logical memory Page number (p) left side of logical address Page offset (d) right side of logical address Page table Page size (frame size) m number of bits (logical address space) n number of bits (page size)

15 No external fragmentation, but internal fragmentation.
1 process No external fragmentation, but internal fragmentation. pp. 329

16 ที่จริงแล้ว page table ก็อยู่ใน memory นั่นเอง ทำให้ทุกครั้งที่โปรแกรมจะ read/write memory ต้องอ่าน page table ก่อน ซึ่งทำให้ช้า Page table is in memory, and it is indexed by PTBR (page-table base register) pp. 328,330

17 m = 4, n = 2 Page size = 4 bytes (locations) 16 locations (1 byte for each) 32 locations (1 byte for each) pp. 330

18 pp. 332

19 ใช้ HW ทำได้ใน O(1) (1) ดูใน TLB ก่อน record ที่ใช้บ่อยๆ จะอยู่ใน TLB
(2) ถ้า miss ค่อย ไปดูใน page table TLB = translation look-aside buffer (in memory) Indexed by PTBR (page-table base register) pp. 334

20 Protection เพื่ม bit เพื่อทำ protection Read-only Read-write
Execute-only ใช้ v และ i เพื่อบอกว่า page ไหนใช้แล้วหรือยังไม่ได้ใช้ จะได้ไม่ต้อง map ทุก page กับ frame มันเปลือง memory pp. 335

21 Create inner page tables on demand.
Hierarchical Paging Create inner page tables on demand. 1 page = 4 KB (212) No hierarchical paging page table = 220 = 1 MB new process = losing 1MB Hierarchical paging new process = 1KB + 1KB Page table = 210 = 1KB Each page table = 210 = 1KB pp. 338

22 Segmentation pp. 343, 345

23 Each segment is of different size.
pp. 344

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